Store Intrinsics

The Intel® Streaming SIMD Extensions 2 (Intel® SSE2) intrinsics for floating-point store operations are listed in this topic. The prototypes for the Intel® SSE2 intrinsics are in the emmintrin.h header file.

The store operations assign the initialized data to the address.

The detailed description of each intrinsic contains a table detailing the returns. In these tables, dp[n] is an access to the n element of the result.

Intrinsic Name	Operation	Corresponding Intel® SSE2 Instruction
_mm_stream_pd	Store	MOVNTPD
_mm_store_sd	Stores lower DP FP value of a	MOVSD
_mm_store1_pd	Stores lower DP FP value of a twice	MOVAPD + shuffling
_mm_store_pd	Stores two DP FP values	MOVAPD
_mm_storeu_pd	Stores two DP FP values	MOVUPD
_mm_storer_pd	Stores two DP FP values in reverse order	MOVAPD + shuffling
_mm_storeh_pd	Stores upper DP FP value of a	MOVHPD
_mm_storel_pd	Stores lower DP FP value of a	MOVLPD

void _mm_store_sd(double *dp, __m128d a)

Stores the lower DP FP value of a. The address dp need not be 16-byte aligned.

*dp
a0

void _mm_store1_pd(double *dp, __m128d a)

Stores the lower DP FP value of a twice. The address dp must be 16-byte aligned.

dp[0]	dp[1]
a0	a0

void _mm_store_pd(double *dp, __m128d a)

Stores two DP FP values. The address dp must be 16-byte aligned.

dp[0]	dp[1]
a0	a1

void _mm_storeu_pd(double *dp, __m128d a)

Stores two DP FP values. The address dp need not be 16-byte aligned.

dp[0]	dp[1]
a0	a1

void _mm_storer_pd(double *dp, __m128d a)

Stores two DP FP values in reverse order. The address dp must be 16-byte aligned.

dp[0]	dp[1]
a1	a0

void _mm_storeh_pd(double *dp, __m128d a)

Stores the upper DP FP value of a.

*dp
a1

void _mm_storel_pd(double *dp, __m128d a)

Stores the lower DP FP value of a.

*dp
a0