Enumerators

The IppStatus constant enumerates the status values returned by the Intel IPP functions, indicating whether the operation is error-free. See section Error Reporting in this chapter for more information on the set of valid status values and corresponding error messages for signal processing functions.

The IppCmpOp enumeration defines the type of relational operator to be used by threshold functions:

typedef enum { ippCmpLess, ippCmpLessEq, ippCmpEq, ippCmpGreaterEq, ippCmpGreater } IppCmpOp;

The IppRoundMode enumeration defines the rounding mode to be used by conversion functions:

typedef enum { ippRndZero, ippRndNear, ippRndFinancial } IppRoundMode;

The IppHintAlgorithm enumeration defines the type of code to be used in some operations: faster but less accurate, or vice-versa, more accurate but slower. For more information on using this enumeration, see Hint Arguments.

typedef enum { ippAlgHintNone, ippAlgHintFast, ippAlgHintAccurate } IppHintAlgorithm;

The IppCpuType enumerates processor types returned by the ippGetCpuType function:

typedef enum {
 /* Enumeration:           Processor:                                */
    ippCpuUnknown = 0x0,
    ippCpuPP,           /* Intel(R) Pentium(R) processor             */
    ippCpuPMX,          /* Pentium(R) processor  
                           with MMX(TM) technology                   */
    ippCpuPPR,          /* Pentium(R) Pro processor                  */
    ippCpuPII,          /* Pentium(R) II  processor                  */
    ippCpuPIII,         /* Pentium(R) III processor 
                           and Pentium(R)III Xeon(R) processor       */
    ippCpuP4,           /* Pentium(R) 4 processor
                           and Intel(R) Xeon(R) processor            */
    ippCpuP4HT,         /* Pentium(R) 4 processor with HT Technology */
    ippCpuP4HT2,        /* Pentium(R) 4 processor with 
                                     Streaming SIMD Extensions 3     */
    ippCpuCentrino,     /* Intel(R) Centrino(TM) mobile technology   */
    ippCpuCoreSolo,     /* Intel(R) Core(TM) Solo processor          */
    ippCpuCoreDuo,      /* Intel(R) Core(TM) Duo processor           */
    ippCpuITP   = 0x10, /* Intel(R) Itanium(R) processor             */
    ippCpuITP2          /* Intel(R) Itanium(R) 2 processor           */
    ippCpuEM64T = 0x20, /* Intel(R) 64 Instruction Set 
                                         Architecture(ISA)           */
    ippCpuC2D,          /* Intel(R) Core(TM) 2 Duo processor         */
    ippCpuC2Q,          /* Intel(R) Core(TM) 2 Quad processor        */
    ippCpuPenryn,     /* Intel(R) Core(TM) 2 processor with 
                                    Intel(R) SSE4.1                  */
    ippCpuBonnell,  				/* Intel(R) Atom (TM) processor */
    ippCpuNehalem,      /* Intel (R) Core(TM) i7 processor
    ippCpuNext,
    ippCpuSSE   = 0x40, /* Processor supports Pentium(R) III 
                           processor instruction set                 */
    ippCpuSSE2,         /* Processor supports Streaming SIMD 
                           Extensions 2 instruction set              */
    ippCpuSSE3,         /* Processor supports Streaming SIMD 
                            Extensions 3 instruction set             */
    ippCpuSSSE3,        /* Processor supports Supplemental Streaming
                           SIMD Extensions 3 instruction set         */
    ippCpuSSE41,        /* Processor supports Streaming SIMD 
                            Extensions 4.1 instruction set           */
    ippCpuSSE42,        /* Processor supports Streaming SIMD 
                            Extensions 4.2 instruction set           */
    ippCpuAVX,        /* Processor supports Intel(R) Advanced Vector 
                            Extensions instruction set               */
    ippCpuAES,        /* Processor supports Intel(R) AES 
                            new instructions                         */
ippCpuX8664 = 0x60,   /* Processor supports 64 bit extension         */
} IppCpuType;

Optimization Notice
The Intel® Integrated Performance Primitives (Intel® IPP) library contains functions that are more highly optimized for Intel microprocessors than for other microprocessors. While the functions in the Intel® IPP library offer optimizations for both Intel and Intel-compatible microprocessors, depending on your code and other factors, you will likely get extra performance on Intel microprocessors. While the paragraph above describes the basic optimization approach for the Intel® IPP library as a whole, the library may or may not be optimized to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include Intel® Streaming SIMD Extensions 2 (Intel® SSE2), Intel® Streaming SIMD Extensions 3 (Intel® SSE3), and Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3) instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Intel recommends that you evaluate other library products to determine which best meets your requirements.

Optimization Notice

The Intel® Integrated Performance Primitives (Intel® IPP) library contains functions that are more highly optimized for Intel microprocessors than for other microprocessors. While the functions in the Intel® IPP library offer optimizations for both Intel and Intel-compatible microprocessors, depending on your code and other factors, you will likely get extra performance on Intel microprocessors.

While the paragraph above describes the basic optimization approach for the Intel® IPP library as a whole, the library may or may not be optimized to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include Intel® Streaming SIMD Extensions 2 (Intel® SSE2), Intel® Streaming SIMD Extensions 3 (Intel® SSE3), and Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3) instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors.

Intel recommends that you evaluate other library products to determine which best meets your requirements.

The IppWinType enumeration defines the type of window to be used by the FIR filter coefficient generating functions:

typedef enum { ippWinBartlett, ippWinBlackman, ippWinHamming, ippWinHann, ippWinRect } IppWinType;

The IppLZ77ComprLevel enumeration defines the compression level to be used by the ZLIB data compression functions:

typedef enum {
IppLZ77FastCompr,
IppLZ77AverageCompr,
IppLZ77BestCompr
} IppLZ77ComprLevel;

The IppLZ77Chcksm enumeration defines what algorithm is used to compute the checksum by the ZLIB data compression functions:

typedef enum {
IppLZ77NoChcksm,
IppLZ77Adler32,
IppLZ77CRC32
} IppLZ77Chcksm;

The IppLZ77Flush enumeration defines what encoding mode is used by the ZLIB data compression functions:

typedef enum {
IppLZ77NoFlush,
IppLZ77SyncFlush,
IppLZ77FullFlush,
IppLZ77FinishFlush
} IppLZ77Flush;

The IppLZ77DeflateStatus enumeration defines the encoding status that is used by the ZLIB data compression functions:

typedef enum {
IppLZ77StatusInit,
IppLZ77StatusLZ77Process,
IppLZ77StatusHuffProcess,
IppLZ77StatusFinal
} IppLZ77DeflateStatus;

The IppLZ77InflateStatus enumeration defines the decoding status that is used by the ZLIB data compression functions:

typedef enum {
IppLZ77InflateStatusInit,
IppLZ77InflateStatusHuffProcess
IppLZ77InflateStatusLZ77Process,
IppLZ77InflateStatusFinal
} IppLZ77InflateStatus;

The IppLZ77HuffMode enumeration defines the encoding mode that is used by the ZLIB data compression functions:

typedef enum {
IppLZ77UseFixed,
IppLZ77UseDynamic,
IppLZ77UsedStored
} IppLZ77HuffMode;

The IppInflateState enumeration defines the decoding parameters that are used by the ZLIB data compression functions:

typedef struct IppInflateState {
const Ipp8u* pWindow; // pointer to the sliding window
// (the dictionary for the LZ77 algorithm)
unsigned int winSize; // size of the sliding window
unsigned int tableType; // type of Huffman code tables
// (for example, 0 - tables for Fixed // Huffman codes)
unsigned int tableBufferSize; //(ENOUGH = 2048) * (sizeof(code) = 4) -
// sizeof(IppInflateState)
} IppInflateState;

The IppInflateMode enumeration defines the decode mode that is used by the ZLIB data compression functions:

typedef enum {
ippTYPE,
ippLEN,
ippLENEXT
} IppInflateMode;

The IppGITStrategyHint enumeration defines which strategy of encoding is used in some operations by the GIT data compression functions:

typedef enum {
ippGITNoStrategy,
ippGITLeftReorder,
ippGITRightReorder,
ippGITFixedOrder
} IppGITStrategyHint;

The IppAffinityType enumeration defines which affinity type is used by the core function ippSetAffinity:

typedef enum {
ippAffinityCompactFineCore,
ippAffinityCompactFineHT,
ippAffinityCompactAllEnabled,
ippAffinityCompactRestore,
ippTstAffinityCompactFineCore,
ippTstAffinityCompactFineHT
} IppAffinityType;